FIG. 1 is a schematic block diagram of a typical ROM device employing an address transition detection (ATD) function. The ROM device includes a memory cell array 10, input buffer circuits 12, 14, 16 and 18, column pass circuit 20, sense amplifier circuit 22, data latch circuit 24, row pre-decoder circuit 26, column pre-decoder circuit 28, ATD circuit 30, short pulse generation circuits 34, 36 and 38, summer 40, and read-out control circuit 42.
Input buffers 12, 14, 16 and 18 receive a chip enable signal, row address signals, column address signals and an output enable signal, respectively, from external circuitry, and convert those external signals into corresponding internal signals CEPi, RAPi, CAPi, and OEi, respectively. Row address signals RAPi and column address signals CAPi generated from row address buffer 14 and column address buffer 16, respectively, are applied to row and column pre-decoders, 26 and 28, respectively, for selecting specific memory cells in cell array 10. Chip enable signal CEPi, row address signals RAPi and column address signals CAPi, from input buffers 12, 14, and 16, are applied to short pulse generation circuits 34, 36, and 38 in ATD circuit 30. Short pulse generation circuit 34 generates and outputs a short pulse signal SPi when the chip enable signal changes states to a high or low state. The short pulse generation circuits 36 and 38 each generate and output short pulse signals RSPi and CSPi, respectively, when at least one of address signals is in a transition state to high or low.
The output pulses of the short pulse generation circuits 34, 36, and 38 are applied to summer 40, which converts the short pulses into one pulse signal SM0 with a predetermined pulse width. The signal SM0 is transferred to the read-out control circuit 42 which generates a precharge control signal PRE and sense-amp control signal SACS in response to the pulse signal SM0 from summer 40.
A precharging operation for bit lines can be performed while the precharge control signal PRE is at an active voltage level. Sense amplifier circuit 22 detects and magnifies voltage levels of data stored in cells of the cell array 10 selected by the pre-decoder circuits 26 and 28, and then transfers the sensed signals to data latch circuit 24. The data held in latch circuit 24 is transferred out of the memory chip through data output buffer circuit 32.
FIG. 2 contains a detailed schematic block diagram of the cell array 10 of FIG. 1. The bit lines are hierarchically composed of main bit lines (MBLs) formed of a conductive metal and sub bit lines (SBLs) formed of a diffused layer. Each of the main bit lines is assigned to two of the sub bit lines, and the sub bit lines are divided in two groups of odd-numbered bit lines and even-numbered bit lines. Memory cells Mmn (m=1,2, . . , I; n=1,2 . . . , I) are coupled to word lines WL1-WLi and the sub bit lines, the gates of the memory cells being connected to the word lines and the drains of the cells being connected to the sub bit lines, in a NOR-type logic, as shown in detail on cells M17 and Mi7. The memory cells may be selectively programmed in a high threshold state of "1" or "off" or in a low threshold state of "0" or "on". The even-numbered sub-bit lines are connected to even-numbered main bit lines through string selection transistors ST0, ST1, . . . . The gates of the transistors ST0, ST1, . . . are coupled to string selection lines SS0 and SS1. The odd-numbered sub-bit lines are connected to odd-numbered main bit lines through ground selection transistors GT0, GT1, . . . . The gates of the transistors GT0, GT1, . . . are coupled to ground selection lines GS0 and GS1.
FIG. 3 contains a detailed schematic block diagram of a configuration of a dummy memory cell in the cell array 10 of FIG. 1. NMOS transistors T1 and T4 correspond to the string selection transistors ST0, ST1, . . . , of FIG. 2. NMOS transistors T2, T5 and T6 correspond to the memory cells Mmn of FIG. 2. The resistances on lines L1 and L2 correspond to the resistances of the sub-bit lines. The NMOS transistors T3 and T7 correspond to the ground selection transistors GT0, GT1, . . . . The dummy cell has current driving capability of half of that of the normal memory cell and is used to provide a reference potential when a corresponding memory cell is selected in a read-out operation.
FIG. 4 is a schematic block diagram of conventional circuitry used during a read-out operation. Referring to FIG. 4, data from a main memory cell array 10 selected by an address is transferred to sense line SL of sense amplifier circuit 22 through a column pass circuit 20 composed of a bit line switching circuit 46 and data line selection circuit 48. A reference line RL of the sense amplifier circuit 22 is connected to the dummy cell array 10 through dummy bit lines such as those shown in FIG. 3. FIG. 5 is a detailed schematic block diagram of a bit line switching circuit 46. The bit line switching circuit 46 responds to selection signals YA0-YAq to electrically connect the main bit lines MBL1, . . . , to data lines DL1, . . . .Each of the selection signals YA0-YAq controls a group of the main bit lines, and the groups are defined in switching blocks 46a, 46b. For example, a high level on YA0 activates a switching block 46a while other switching blocks are held in an inactive state because their selection signals are not enabled.
The number of main bit lines assigned to a switching group is variable according to an output data format. For example, an 8-bit memory device can have eight main bit lines in one switching block, and a 16-bit device can have sixteen main bit lines in a switching block. The number of the data lines, DL1-DL8, for example, is also compatible with the number of main bit lines in the block. In each of the switch blocks 46a, 46b, . . . , NMOS transistors SWTi0-SWTi7 are interposed between their corresponding main bit lines and data lines. The gates of the transistors in a block 46a, 46b, . . . are coupled to their corresponding selection lines YA0-YAq, as shown. Hence, a group of main bit lines is selected for connection to the data lines DL1-DL8 by a signal YA0-YAq, and the data lines are connected to a data line selection circuit 48, which selects one of the data lines to be transferred to the SL input of the sense amplifier 22.
FIG. 6 is a detailed schematic block diagram of data line selection circuits 48a and 48b. Each of the selection circuits connects one of data lines DL1-DL8, corresponding to a selected memory cell, to sense amplifier circuit 22. Each circuit 46a, 46b also grounds data lines adjacent to the selected line and connects the other non-selected data lines to a bias line L3. One selection circuit 48a connects one of the even-numbered data lines DL2, DL4, DL6, DL8 assigned to its corresponding main bit lines to sensing line SL in response to selection signals DLS0, DLS1, DLS2 and DLS3. The second selector 48b connects one of odd-numbered data lines to ground.
The first selector 48a is connected to the even-numbered data lines DL2, DL4, DL6 and DL8, and includes inverters IV1, IV2, IV3 and IV4, corresponding to the even-numbered data lines, and NMOS transistors T8-T15. The pairs of the NMOS transistors, T8 and T9, T10 and T11, T12 and T13, and T14 and T15, are each connected between sensing line SL and bias line L3 in series, with common source nodes coupled to their corresponding data lines DL2, DL4, DL6 and DL8. Gates of the NMOS transistors T8, T10, T12 and T14 are each coupled to selection signals DLS0-DLS3, respectively. The drains of the transistors T8, T10, T12, and T14 are connected to sensing line SL which is connected to the sense amplifier circuit 22. The gates of NMOS transistors T9, T11, T13 and T15 are coupled to inverted signals of the selection signals DLS0-DLS3. The drains of the transistors T9, T11, T13 and T15 are connected to bias line 13.
When the selection signal DLS0, for example, is switched to a high state while DLS1, DLS2, DLS3 are maintained in a low state, NMOS transistors T8, T11, T13 and T15 are switched on while NMOS transistors T9, T10, T12 and T14 are switched off. As a result, the selected data line DL2 is connected to the sensing line SL while the other data lines DL4, DL6 and DL8 are connected to bias line L3.
The second selector 48b is connected of the odd-numbered data lines DL1, DL3, DL5 and DL7 and includes inverters IV5-IV8, corresponding to the odd-numbered data lines, and NMOS transistors T16-T23. The pairs of the NMOS transistors, T16 and T17, T18 and T19, T20 and T21, and T22 and T23, are each connected between the bias line L3 and ground in series, with common source nodes coupled to their corresponding data lines, DL1, DL3, DL5 and DL7. Gates of the NMOS transistors T16, T18, T20 and T22 are each coupled to selection signals GDL0-GDL3, respectively. The drains of the transistors T16, T18, T20 and T22 are connected to the bias line L3. The gates of the NMOS transistors T17, T19, T21 and T23 are coupled to inverted signals of the selection signals GDL0-GDL4, respectively. The drains of transistors T17, T19, T21, and T23 are connected to ground. When the selection signal GDL0, for example, is switched to a high state while GDL1, GDL2, and GDL3 are maintained in a low state, NMOS transistors T16, T19, T21 and T23 are switched on while NMOS transistors T17, T18, T20 and T22 are off. As a result, data line DL1 can be connected to bias line L3. Since NMOS transistors T17, T18, T20 and T22 are turned on while NMOS transistors T16, T19, T21 and T23 are off when GDL0 is in a low state and GDL1, GDL2, and GDL3 are high, a selected data line DL1 can be connected to ground while the other data lines DL3, DL5 and DL7 are connected to bias line L3.
FIG. 7 is a detailed schematic block diagram of a sense amplifier circuit 22. The sense amplifier circuit 22 is connected to sensing line SL, which is connected to a selected data line by the data line selection circuit 48, as described above in connection with FIG. 6 and a dummy data line (or reference line) DDL which receives a reference voltage from a dummy cell as shown in FIG. 3. The sense amplifier 22 also includes a first precharge circuit 52 for charging a corresponding main bit line during a bit line precharge cycle, a second precharge circuit 54 for charging a corresponding dummy bit line during a bit line precharge cycle, current-mirror-type differential amplifier 56, and first and second bias circuits 58 and 60.
The precharge circuit 52 includes four NMOS transistors, T30, T32, T33 and T34, and two PMOS transistors T29 and T31. NMOS transistor T30 is connected between a power supply and an input node N1 connected to the differential amplifier 56. The gate of T30 is coupled to precharge control signal PRE generated from the ATD circuit 30 of FIG. 1. PMOS transistor T29 is connected between a power supply and input node N1. The gate of T29 is also connected to node N1. NMOS transistor T33 is connected between input node N1 and sensing line SL. NMOS transistor T34, the gate of which is coupled to sensing line SL, is connected between the gate of NMOS transistor T33 and ground. NMOS transistor T32, the gate of which is coupled to complementary signal SACSB of sense amp control signal SACS generated from the ATD circuit, is connected between the gate of NMOS transistor T33 and ground. PMOS transistor T31, the gate of which is coupled to SACSB, is connected between the power supply and the gate of NMOS transistor T33.
The transistors T29 and T30 act as current sources for driving a predetermined amount of current into a main bit line during the bit line precharge cycle, and the transistors T31 through T33 cause voltage levels of their corresponding main and sub bit lines to be compared to a threshold level of T34.
Precharge circuit 54 includes four NMOS transistors T35, T38, T39 and T40 and two PMOS transistors T36 and T37, analogous to the transistors of the precharge circuit 52. NMOS transistor T35, the gate of which is coupled to precharge control signal PRE generated from the ATD circuit 30 of FIG. 1, is connected between a power supply and input node N2 connected to the differential amplifier 56. PMOS transistor T36, the gate of which is coupled to node N2, is connected between a power supply and input node N2. NMOS transistor T40 is connected between input node N2 and reference line RL (or dummy data line DDL). NMOS transistor T39, the gate of which is coupled to reference line RL, is connected between the gate of NMOS transistor T40 and ground. NMOS transistor T38, the gate of which is coupled to SACSB, is connected between the gate of NMOS transistor T40 and ground. PMOS transistor T37, the gate of which is coupled to SACSB, is connected between the power supply and the gate of NMOS transistor T40.
The transistors T35 and T36 act as current sources for driving a predetermined amount of current into a main bit line during the bit line precharge cycle, and the transistors T37 through T40 cause voltage levels of their corresponding main and sub bit lines to be compared to a threshold level of T39.
Differential amplifier 56 includes a pair of PMOS transistors T24 and T25, NMOS transistors, T26 and T27, each connected to T24 and T25, and NMOS transistor T28 connected between a common node of T26 and T27 and ground. T26 and T27 are typically fabricated to have identical electrical properties. The gate of T26 is coupled to reference line RL (or dummy data line DDL) through T40. The gate of T27 is coupled to sense line SL (or data line DL) through T33. The gate of T28 is coupled to sense amp control signal SACS.
A first bias circuit 58 includes two NMOS transistors T41 and T43 and PMOS transistor T42. NMOS transistor T41, the gate of which is coupled to precharge control signal PRE, is connected between the power supply and node N3. The source of PMOS transistor T42, whose gate and drain are connected in common at node N3, is connected to the power supply. NMOS transistor T43, the gate of which is coupled to the drain of T34 of the first precharge circuit 52, is connected between node N3 and bias line L3 of the data line selection circuit 48.
The second bias circuit 60 is formed of two NMOS transistors T44 and T46 and PMOS transistor T45. NMOS transistor T44, the gate of which is coupled to precharge control signal PRE, is connected between the power supply and node N4. The source of T45, whose gate and drain are connected in common at node N4, is connected to the power supply. NMOS transistor T46, the gate of which is coupled to the drain of T39 of the second precharge circuit 54, is connected between node N4 and bias line L3 of the data line selection circuit 48.
The read-only memory described above in connection with FIGS. 1-7 requires one dummy data line (or reference line) for one sense amplifier circuit in order to detect data stored in a memory cell selected by address signals. The number of the sense amplifier circuit and dummy data lines is generally determined by the type of data-out module employed in a memory, e.g., one-of-eight, one-of-sixteen, one-of-thirty-two. Such a direct increase in the number of the dummy data lines with respect to the number of sense amplifier circuits may cause the area occupied by a memory cell array to be increased, resulting in difficult circuit design and decreased integration density.